SystemVerilog editor features

Edaphic Studio smartly supports expected IDE editor features like code completion, formatting, and folding. With the analysis engines understanding of SystemVerilog syntax and the current project, it can provide powerful and smart options for each feature. Scroll down to learn more.


Code Completion

Built-in scope traversal automatically builds up a list of relevant auto-complete targets. It understands all SystemVerilog hierarchies like class, module or packages. As a result, your choices for code-completion are always appropriate. You can use the up and down arrows to select the correct target then hit tab for completion. Auto-completion uses fuzzy matching logic. No need to remember the function name exactly. Type what you remember and Edaphic.Studio will sort it out.

Please take a look at the examples below to see what Edaphic.Studio can do.


Code Formatting

Edaphic.Studio formats SystemVerilog code. Formatting is more than indentation it defines allowed spacing between code objects as well as the alignment for multiple lines of the same type (like variable declarations).

Formatting is a personal preference and Edaphic.Studio has several settings for formatting allowing you to find a style that works for you and your company.

 
 

Automatic Header File view

EdaphicStudio supports Structure View ([ALT][7]) that brings up a code summary window. We like to think of it as an automatic header file view as it is an excellent way to see all functions, tasks, and variables available for a class but it also works as well for modules, packages, and programs.

 

Structure View example

 

Folding

Edaphic Studio supports folding of almost any code block be it a module instantiation, port list declaration, function etc. Simply click on the fold marker in the left gutter (see image) to fold. If you hover over a folded block you get a quick glance of contents. Simply clicking on a folded block will expand it again.

 

Code folding

 

Smart Ligatures

Edaphic.Studio smartly supports ligatures for SystemVerilog. It will suppress ligatures for nonblocking and clockng assignment keeping your code easy to read!

Easy to read ligatures on line 6. Suppress on nonblocking and clocking assignment lines.