Before you can start using Edaphic Studio and IntelliJ you need to define a project file which describes the files you are using for the scope you are currently working on. Using project files is typical for any IDEs and allows the editor to make more intelligent suggestions. A project file defines a specific configuration, breaking the overall program into more manageable pieces. For ASIC and FPGA designs a specific project file tends to correspond to a specific testbench configuration.
There is much documentation about project files on IntelliJ's website, but most of it is Java specific. Below is documentation for how to work with project files for SystemVerilog projects.
Edaphic Studio will, with the knowledge from the project file, analyze all SystemVerilog code and dynamically build the project hierarchy. This knowledge allows you to navigate your code with ease, rename variables, classes and modules throughout a project and provides smart code completion.
Creating a project file is not hard and easiest done by importing an existing project. The following pages give two project examples. The first example shows how you can work with UVM for your project. The second example shows how you can solve multiple file conflicts within a project. Both examples are available to clone on GitHub so that you can follow along.
Edaphic Studio is at the moment using IntelliJ's default project file structure. We will in the future move to our EDA specific project structure, emulating simulator command files, which will allow solving compile order complexities and setting global defines. This documentation will be updated to reflect that change.