2018.3.BETA.1: Improved error messages, formatting and macros

Today a new BETA of the SystemVerilog plugin was released. This release dramatically improves how soon code is matched to SystemVerilog rules and includes a complete rewrite of the assertion rules. The most noticeable effect will be better error messages, but it also helps with indentation and formatting (which all uses the underlying rules). These improvements are needed to support keyword code-completion. Unfortunately, keyword code completion requires more time before it's ready for early release.

Better macro view

The most visible addition in this release is that expanded macro code is now formatted and highlighted when you hover over a macro:

Structure view [CTRL-7] on the left & improved macro expansion on the right.

The goal is to include any error messages in the expanded code area, but to do that requires a rewrite of the pre-compiler engine (see below).

Formatting improvements

Formatting continues to improve. With this release, the formatter no longer break defines by inserting a space between the name and the (.

Formatting is now stricter about spaces between operators and parenthesis sign and now knows how to format enums.

Finally, data declarations do not get aligned across blocks. Alignment is a work in progress. Currently, too many items get aligned which works well for a specific coding style but not across some examples. I'm also not a massive fan of aligning objects as I don't think it aides in reading code (though it looks pretty impressive). So for the next couple of releases alignment will be toned down and later re-enabled as an option.

I'm sure you have opinions of what should be aligned and formatting in general. Please let me know your thoughts and where the plugin falls short.

Other improvements:

  • Fixed “Move variable declaration to before statement” quick-fix corner case: It will now correctly move data declarations to before macro statements as needed.
  • Resolve of enums inside constraints now works
  • String concatenation used as arguments to macros now works.
  • Structure view [CTRL-7] no longer prints null or empty messages for objects inserted by macros. In a future update, it will correctly list these items.

Next steps

Here is what's being worked on at the moment:

Code Completion:

Work is progressing on keyword code-completion. Now keyword code completion might sound like an easy thing - present a list of keywords and be done with it. IntelliJ's intent with code-completion is to only present valid options. So if code-completion is not offering a particular choice, then this option is (probably) not correct. Enabling code-completion like this takes a more effort but also provides more value.

Teaser shot of upcoming code completion. Hopefully released soon!

Currently, first-pass code-completion works for modules, which, with generate blocks and other logic is a surprisingly large part of the specification. Code completion will be enabled when it works for sequential code (i.e., blocks, functions, tasks, etc.) and class items.

Pre-Compiler improvements

The pre-compiler needs to be updated. The current implementation is slow and made some incorrect assumptions on how IntelliJ works. This sluggish performance is an issue when editing large UVM files with lots of macros.

A new implementation has been defined and will implementation is starting.

Beta9: #SystemVerilog interface classes added

Today a new release of the SystemVerilog plugin was released. It solves a couple of issues reported by users. It adds support for interface classes (including formatting and resolve), adds a workaround for dealing with global defines and improves formatting by leaning on guidelines from SystemVerilog.io. More on each issue below.

I would much appreciate if you share this post or a link to the website with anyone you think would be interested. I need to reach more users to help show that there is a market for a product like this. With enough support, we can take this plugin to the next level and develop it faster!

I want to become CLion but for EDA - a front-end IDE able to work with all existing tool-chains . With you and your company’s support we can get there! Thank you!


Interface classes

Interface classes is a new(-ish) concept in SystemVerilog. I have personally not seen it used anywhere and I'm not sure how well supported it is. Still, I support the idea!

You can tell interface classes was a late addition to the SystemVerilog specification as it's floating free (not referenced by any other rule) in the formal syntax (Appendix A). In other words, going by the spec, you can't reach these rules! At least as far as I can tell.

Interface classes is an intriguing idea borrowed from Java (and Kotlin) that could help when building class libraries like UVM. It's somewhat akin to multiple-inheritance but with less power and fewer pitfalls.

With interfaces, a new DV environment could say "Your sequence object fits into my DV environment as long as you follow the IVM-sequence contract." Then as a DV engineer, I would have to make sure my object follows the IVM-sequence contract by implementing all tasks and functions required.

There are even ways of doing partial implementations that would reduce the number of functions that need implementation.

I think interface classes could improve the UVM library by reducing the over-reliance on macros that implement multiple functions needed by the UVM engine. Implementing UVM using interfaces would clarify to users how it all connects and remove the hassle of dealing with macros.

I'd love to see such an implementation! Please reach out to me if you are using interfaces. Today I fully support the syntax, formatting, and resolution but I'd love to add interface checking directly in the editor. It's quite doable but the list of urgent task is long, and I will only get around to interface class checking if there is a demand.

A workaround for global defines

The SystemVerilog plugin is currently not aware of compile-order or global defines (i.e., defines passed in on the command line). To support these features, a new build environment is needed. A build environment is high on the list of features to add, but until then we now provide a workaround.

There is now a single global define assumed by the plugin. It's called edaphic and is defines as define edaphic 1. You can use this define to wrap code inside conditional compilation directives (i.e.ifdef) that only my plugin will read. In this way, you can make edaphic studio aware of global run-time defines as needed without affecting your builds.

Below is an example of how you can use it. In this example, the file edaphic_global_defines.svh will only be read by the editor and it is used to set up global definitions. At compile time this extra code is ignored since edaphic is not defined then. I hope this helps to pass in global defines as needed. It's not ideal which is why it's called a workaround. With your support, I hope to implement a real build environment soon!

Better formatting

Formatting is essential and a feature I worked hard to make work. A format includes spacing, indenting and aligning objects. The goal is to make your code as readable as possible. The initial approach was to be very permissible, but that leads to poorly formatted results. I recently found SystemVerilog.io’s Style Guide, and it gave me the courage to implement stricter formatting based on its suggestion. This release is only a start, but the end goal is to format code as per the site's recommendations by default while also providing customization options.

reformat code.gif

Formatting of SystemVerilog is hard. It's not a beautiful language, and there are many places where there are no great formatting options (I'm looking at you multi-line module header that makes indenting the module body awkward).

Formatting differs from company to company, project to project and person to person. Please let me know any places where you disagree with the plug-ins formatting, and I will do my best to fix it or provide customization options.

My goal is to tighten up formatting little by little with each release.

What's next?

The issues solved with this release got me sidetracked from implementing keyword code-completion and better highlighting colors. They are still next on the list of new features to add as they are much needed. However, there are also many new issues reported and solving critical issues takes priority so please keep reporting issues!

Beta8.1: Fix for reoccuring crash when working with UVM

Unfortunately, release 8.0 exposed a crashing bug in the plugin, seen most often when working with UVM projects. Not an expected or acceptable plugin behavior and I apologize for letting it slip through. Will pay more attention to occasional crashes going forward.

The only good news is that this solution solves a lot of occasional crashes. The cause was the Compiler Directives logic breaking against the @NotNull identifier contract. The answer is to modify contract and code to handle null for any identifier.

I have asked JetBrains' for expedited approval and hope to see the fix released shortly! Will update this post when they do.

Please keep reporting issues!

SystemVerilog Beta8: Macros & code-completion

UVM macros & variable code-completion

This release fixes a couple of issues with define and macro compiler directives and enables scoped code-completion for variables and objects.

  • Fix for #8 an issue with code completion for module, interfaces, and package
  • Fix for #12 an issue with inline contraints in defines (i.e foo.randomize() with ...)
  • Fix for #13 an issue with expansion of cross-file nested defines

The compile directives issues made UVM macros not expand correctly and also incorrectly reported syntax errors in some cases. Read on to see UVM macros like you have not seen them before :-)

This release also enables scoped based code-completion for all code objects. Code-completion happens automatically as you type [Ctrl]+[Space] also invokes it (with a more in-depth search). I need your help to track down issues! First, please look for places where code-completion doesn't work and report it. Secondly, code-completion is bare bones at the moment. It does respect scope but doesn't look for other clues so please report examples where code-completion suggest incorrect options - for example a module reference inside a function. It's relatively easy to restrict what code-completion reports depending on the scope, but I need help with examples!

UVM macros like you haven't seen them before!

One of my pet-peeves with UVM is its over-reliance on macros. I can't for the life of me remember what all the UVM macros do and trying to parse through them is head-ache inducing. There are macros within macros within macros! Argh!

With this release, Edaphic Studio supports UVM macros better. Just hover over any macro to see the actual expanded code the macro generates. Like this:

This expansion happens while you type and errors are reported directly in the editor. Take a look at this example video for details:

A common issue with macros is cryptic syntax error messages - linking errors back to provided arguments is hard. Edaphic Studio error messages are no better than your compiler at the moment, but at least the error checking is done live as you type. Advanced Live error checking saves compile cycles!

Finally here is a short video highlighting my issue with UVM. There has to be a better way to implement whatever this is! At least my editor provides some clues to what it does if you happen to forget:

UVM sure like macros! With Edaphic Studio you can hover over any macro to see resulting code. We use the expanded code to check for syntax errors!

Advanced live syntax checking is one-way Edaphic Studio makes coding more natural and efficient. You will spend less time looking at compiler error messages!

SystemVerilog Editor Beta 7: Fix module rename crash & improved code-completion

On Sunday a new beta of my SystemVerilog plugin was released. It contains two critical fixes. First, it fixes a crash when renaming modules and secondly it drastically improves code completion (and performance) for sequential code.

The update automatically downloaded for all users who can choose to upgrade when appropriate.

How to rename any object in a project

The Edaphic Studio SystemVerilog plugin has a powerful feature for renaming any object across files in a project. It's an important feature that I believe you will find very useful so In this section, I wanted to show how to use it.

Having to rename an object used throughout a project can be a pain. I know from experience that many of us hesitate to do it as it takes many compile-fix-error cycles to get it right. Waiting to rename an object is especially true if the object has a generic name like "clk," "reset_n" or "i." We tend to live with old names which lead to confusion.

With the Edaphic Studio SystemVerilog plugin renaming any object, is easy to do. Just move to the definition of the object (Ctrl-B), enter rename mode (Shift-F6), change the object's name and exit rename mode (Shift-F6 again). This rename all usages of the object across the system.

_It's important to realize that this work even if you are trying to rename something generic like clk,``reset_n or i. The SystemVerilog plugin only renames usages of the chosen object by analyzing the scope and hierarchy tree to find actual usages. Rename is not a simple search-and-replace script!_

Once you get used to it, I think you will use it a lot.

It's a feature that makes coding more manageable, so I created a small video for it and a step-by-step example below.

You can try it out by using the Truss project example and following these steps:

  • Go to the uart_top declaration by using the search-anywhere command [double shift]; typing "uatop" and picking the uart_top class (in uart_top.v):
  • Optional! List all usages by using Ctrl-B:
  • With the cursor on uart_top enter rename mode using Shift-F6. This highlights the current variable in a red box. Rename the variable to uart_16550_top:
  • Exit rename mode with Shift-F6. This brings up a confirmation window (where you can optionally choose to search and update comments). Click Refactor or simply hit Enter:
  • Optional! Use Ctrl-B again to confirm name changes.

So renaming any object is as easy as entering rename mode (shift-F6), changing the object name and exiting rename mode (shift-F6). It's a feature I think you will find instrumental.

You can undo a rename with Ctrl-Z which reverts the name change across affected files.

Happy Coding!

Better code-completion inside sequential code

This release fixes code completion issues inside any sequential code. The problem was highlighted in issue #9. This fix will make day to day coding much better! We hope you enjoy it.

The fix was somewhat involved, so for the interested here is a more in-depth explanation:

The #9 code-completion issue forced a much needed but large optimization of the statement rule detector logic. The core issue was that just typing an identifier didn't match any specific rule as it matched many. None of these matches had enough information to say - I'm it.

When no rule matches then no code completion happens since code completion is content aware and only completes for objects in scope.

The solution was to restructure the statement detector to unify all rules that can start with an Identifier into a single master rule. SystemVerilog has a lot of rules that can do that! This change improves not only code-completion but also error messages, error recovery and overall performance.

There is a similar optimization needed for modules #8. If you find other places where code-completion doesn't automatically work, please let me know, and it will get updated. Having smart code-completion working is a high-priority issue.

Next release

The next couple of releases will continue to deal with code-completion. Focusing first on getting variable name code-completion to work reliably everywhere. The following completion improvement will be for code in module space (see #8 for details). If you find places where code-completion doesn't happen, please file issues, and I will get to them as soon as possible.

Once variable code-completion works reliably, then keyword completion will be added. This feature is a comparably simple task but still needs to smarts to only show keywords relevant to your scope.

New SystemVerilog Editor 2018.2.Beta6 Released. Looking for more users!

New SystemVerilog Editor 2018.2.Beta6 Released. Looking for more users!

Edaphic Studio tries to make coding easier. Now we're smarter about how we handle begin/end blocks - automatically inserting end and labels information as you type. This feature should make coding a little easier as you don't have to remember closing blocks while the editor is smart enough to no get in your way. We hope you like it. The goal is to make all paired keywords work similarly. We think you will like it and would **love your feedback**! We prepared [a short video](https://vimeo.com/290704513) highlighting this feature.

Beta 5 Releases Notes: 2018.2 bug fix & Automatic Header file view

Plugin integration issue solved

This release fixes an issue with a JetBrains code change in 2018.2 that caused crashes for our SystemVerilog plugin. The SystemVerilog plugin is once again available on the "app store" for the latest IntelliJ releases. We learned two lessons: First, from now on, we will actively test upcoming IntelliJ releases to detect issues like this before they are released. Secondly, it highlights the need for a stand-alone Electronic Design IDE where we can better control for quality. It has always been on our list of essential features, but this issue brought it home.

IntelliJ based products do not have built-in support for plugins that require C/C++ like macro support. So to support SystemVerilog Compiler Directives (i.e., defines and macro resolution) we had to integrate more deeply with the IntelliJ code base than a standard plugin. This deep integration leaves our plugin somewhat sensitive to changes in the IntelliJ code. Finding and understanding the impact of an IntelliJ code change also took longer than anticipated. From now we will try to test against upcoming releases so that we are not caught off-guard again.

Having support for resolving macros and checking the underlying code is essential for a SystemVerilog IDE otherwise static analysis is not possible. We are actively working to improve this feature with many planned upgrades.

We sincerely apologize for the inconvenience this bug caused and will work hard to ensure this does not happen again.

With that said we would now like to talk about something positive - automatic header files!

Structure View - an automatic header file for SystemVerilog!

With this release, the SystemVerilog plugin now supports the Structure View feature. The structure view is a quick way to get an overview of the current file. It can be thought of as an automatic header file and can be useful for understanding large SystemVerilog classes etc. To bring up Structure View use [ALT][7] on Linux and Windows and [COMMAND][7] on mac.

With this feature, the SystemVerilog plugin now supports all essential JetBrains Editor features. Now starts the real work adding great checks in tool integration to take the experience to the next level. The structure we have in place will allow us to add meaningful checks, automatic fixes and suggestions to really reduce compile errors, check and fixes for common code mistakes and much more. We think you will like it.