Enabling smart ligatures

Ligatures replace multi-character symbols like != and >= with corresponding multi-width glyphs. These ligatures make your code easier to read and reduces the mental burden of translating combinations of characters into their meaning. It's surprisingly effective.

Unfortunately, SystemVerilog uses the <= data-preserve-html-node="true" to mean less than or equal to or assign for nonblocking (and clocking) statements. Edaphic Studio can smartly suppress ligatures as needed for these assignments.

JetBrains doesn't currently offer a way to disable ligature generation per code object. The suggested way to suppress ligature generation is to change the color of specific characters slightly.

To enable this color change and smart suppression, you must do a one-time setup for each color-scheme you use. Follow the instructions below to enable smart ligatures for the default JetBrains and Material Theme UI colors schemes. If you use a custom color scheme follow the instructions here.

We think this one-time setup is worth it!

Here is what smart suppression of ligatures looks like.

Ligature used on line 6 and suppressed on the assignment lines (7,10,12)


Open font preferences

Open Font preferences

To use ligatures, you need to use a supported font. JetBrains ships with a font called Fira Code which supports ligatures. There are other fonts available. We use the font "Pragamata Pro" in our screenshots which costs money.

To enable ligatures in JetBrains:

  1. Open the "run any command" search bar by using keymap [Ctrl][Shift][A] on Linux and Windows and [Command][Shift][A] on Mac.
  2. Type "font" in the search bar then select "Font Preferences" as in this picture

Enable ligatures

Enable Ligatures globally

  1. Make sure to select Fira Code or another compatible font
  2. Make sure the "Enable font ligatures" checkbox is selected.
  3. Click Ok.

SystemVerilog Color Scheme Settings

Open SystemVerilog color scheme settings

To enable smart suppression of ligature for nonblocking assigns, you need to go through the following steps for each color scheme you use.

We have listed correct settings for the default JetBrains colors schemes as well for all Material Theme UI schemes. At the end of this article, we show how to figure out the correct setting for other color schemes.

Use [Ctrl][Alt][S] on Linux and Windows to open the Settings dialog. On Mac use [Command][,] to open the preference pane.

  1. Select Editor -> Color Scheme -> SystemVerilog in the left pane.
  2. Select the "Intelligent Ligature Setting"
  3. Uncheck the "inherits values from" checkbox.
  4. Uncheck the "italics" checkbox.
  5. Click the Foreground color value. A pop-up window opens.

Color chooser

Set correct Foreground color

  1. In the pop-up window change the color value to a value from the table below.
  2. Click Choose
  3. Click "Ok" in the main preference window to save settings

Foreground color values

JetBrains

  • Default: Foreground 000001
  • Darcula: Foreground A9B7C7

Material Themes UI

  • Arc Dark: Foreground A7A7A8
  • Atom One Dark: Foreground A6B2C1
  • Material Darker: Foreground 89DDFE
  • Material Lighter: Foreground 39ADB6
  • Material Monokai Pro: Foreground 86DDEA
  • Material Oceanic: Foreground 86DDEA
  • Material Palenight: Foreground 89DDF8
  • Material Solarized Dark: Foreground 839497
  • Material Solarized Light: Foreground 586E76

Smart ligatures

Check that your settings are working

If you want to check that smart ligatures are working then create a scratch file with the following content.

`define TCQ 100

module issue;
    always @(posedge clk) begin

        if (a <= 3) begin
            diff_pntr <= 0;
        end else begin
            if (wr_en)
                d <= #100 (x - y + 2'h1);
            else if (wr_en)
                d <= #`TCQ (x - y);
        end
    end
endmodule

Verify that ligatures are generated for the if statement but not for the blocking assignment.

To create a scratch file use [Ctrl][Shift][A] on Linux and Windows and [Command][Shift][A] on Mac and type "scratch file". Then select SystemVerilog.