Compiler Directive Macro example:

In this example, we go through step-by-step how the Edaphic Studio analysis engine works with Compiler Directives. This example shows how much analysis the built-in engine does behind the scenes while you are editing.

The editor displays two SystemVerilog files in the screen-shot to the right: uart_16550_sfm.sv on the bottom and uart_16550_registers.sv on the top.

You can click in the image to expand it.

1: While analyzing the uart_16550_sfm.sv file the engine finds the macro field_get. Through include path analysis, it knows that the source of field_get is in uart_16550_registers.sv. 2: It retrieves the field_get definition and substitutes the fields into the this code

data[`interrupt_id_max:`interrupt_id_min]

3: The resulting code contains two new macros, interrupt_id_max and interrupt_id_min which the engine looks up in the same file. 4: The resulting code is now data[3:1] with no additional nested macros. This result is used to check the syntax in the original file (uart_16550_sfm.sv) and is displayed when the cursor hovers over the macro. 5: Using data[3:1] in the if statement results in correct SystemVerilog code so after analyzing the rest of the uart_16550_sfm.sv a green check-mark is displayed

This code analysis is done on-the-fly and without relying on any external tools. It just works on all platforms.